Input/output (I/O) circuits are typically arranged in cells at the periphery of integrated circuit chips, and interface between a chip's core and the external world. I/O cells usually include a driver to transmit digital signals and a receiver to receive digital signals. In integrated circuits that use multiple supply voltages, the I/O cells often must work with at least two supplies to support compatibility with the legacy standards. If the maximum operating voltage of the I/O cell's transistors are compliant to one voltage domain, they are expected to work in higher voltage domains to support industry interface standards as well as meet their own timing, slew control and other requirements of I/O specification.
To operate the I/O cell's transistors in safe tolerable regions without causing any reliability issues like Gate-Oxide Breakdown, Hot Carrier Electrons (HCE), Negative Bias Temperature Instability (NBTI) and Electro-migration, there are a few conventional techniques. Such techniques include stacking of transistors, reference voltage generation, and process/voltage/temperature (PVT) independent design topologies. These solutions typically employ voltage dependent biasing of the transistors. In multi-voltage operation, however, a common problem with such voltage dependent biasing is that the transistors experience asymmetric behavior with voltage variation. This causes multiple performance issues including transistor drive strength mismatch, slew rate offset, duty cycle distortion (DCD) and unoptimized silicon area, to name a few.
In the following description, the use of the same reference numerals in different drawings indicates similar or identical items. Unless otherwise noted, the word “coupled” and its associated verb forms include both direct connection and indirect electrical connection by means known in the art, and unless otherwise noted any description of direct connection implies alternate embodiments using suitable forms of indirect electrical connection as well.